RTL Developer — AI ASIC Accelerator
<p><b>Salary: £66,000 - 106,000 per year</b></p>
<b>Requirements:</b>
<ul><li>7+ years of experience in RTL design and ASIC development</li><li>Strong proficiency in Verilog/SystemVerilog</li><li>Hands-on experience across the entire chip development lifecycle</li><li>Proven expertise in complex IP integration (e.g., multi-core CPUs, NoCs, GPUs/NPUs, or high-speed interfaces like PCIe, 100/400G Ethernet, UCIe)</li><li>Experience writing specifications and converting them into robust designs</li><li>Deep understanding of multiple clock domains and asynchronous interfaces</li><li>Familiarity with AMBA bus protocols (AXI, AHB, APB)</li><li>Experience in power and clock management design</li><li>Proficiency with formal equivalency checking (RTL ↔ Netlist)</li><li>Experience with DFT implementation</li><li>Strong scripting skills (Tcl, Python) for automation and timing/debug flows</li></ul>
<b>Responsibilities:</b>
<ul><li>Lead the end-to-end design of complex ASIC subsystems, including specification, architectural exploration, IP evaluation/selection, integration, verification planning, and post-silicon validation.</li><li>Drive architecture and micro-architecture trade-offs across features, performance, power, and area.</li><li>Define clean interfaces and deliver production-quality RTL (Verilog/SystemVerilog).</li><li>Implement and verify designs at both block and subsystem levels (using UVM/formal as needed); set coverage goals and drive sign-off.</li><li>Define constraints and close timing: author SDC, run STA (setup/hold, OCV/derates), perform CDC/RDC analysis, and collaborate with PD on floorplanning and CTS.</li><li>Perform simulation and emulation (FPGA/emulator), debug waveforms/logs, and correlate pre- and post-silicon behavior.</li><li>Define and implement DFT/DFD strategies (scan, MBIST/LBIST, boundary scan/JTAG); support ATPG and test bring-up.</li><li>Maintain high code quality with lint, CDC/RDC, LEC, and synthesis-friendly design practices; manage ECOs where necessary.</li><li>Build automation flows: develop Tcl/PrimeTime scripts for skew analysis, clocking, and core-to-IO interfaces (PCIe, 400GE, UCIe).</li><li>Write clear specifications, micro-architecture docs, and user guides for downstream engineering teams.</li></ul>
<b>Technologies:</b>
<ul><li>AI</li><li>Ethernet</li><li>FPGA</li><li>Firmware</li><li>Support</li><li>PCIe</li><li>Python</li><li>SystemVerilog</li><li>Verilog</li><li>Flow</li><li>Linux</li><li>Security</li></ul>
<p><b>More:</b></p>
<p>We are seeking a Senior ASIC Design Engineer to own the end-to-end design of critical AI ASIC subsystems. The RTL you create will become production silicon, powering real-world AI workloads faster and more efficiently. In this role, you will collaborate closely with silicon architects, verification engineers, firmware engineers, and other teams to ensure design robustness and optimize workload mapping. We value deep RTL mastery and the ability to integrate complex IP while driving architectural decisions in our innovative environment.</p>
<p>last updated 8 week of 2026</p>
<b>Requirements:</b>
<ul><li>7+ years of experience in RTL design and ASIC development</li><li>Strong proficiency in Verilog/SystemVerilog</li><li>Hands-on experience across the entire chip development lifecycle</li><li>Proven expertise in complex IP integration (e.g., multi-core CPUs, NoCs, GPUs/NPUs, or high-speed interfaces like PCIe, 100/400G Ethernet, UCIe)</li><li>Experience writing specifications and converting them into robust designs</li><li>Deep understanding of multiple clock domains and asynchronous interfaces</li><li>Familiarity with AMBA bus protocols (AXI, AHB, APB)</li><li>Experience in power and clock management design</li><li>Proficiency with formal equivalency checking (RTL ↔ Netlist)</li><li>Experience with DFT implementation</li><li>Strong scripting skills (Tcl, Python) for automation and timing/debug flows</li></ul>
<b>Responsibilities:</b>
<ul><li>Lead the end-to-end design of complex ASIC subsystems, including specification, architectural exploration, IP evaluation/selection, integration, verification planning, and post-silicon validation.</li><li>Drive architecture and micro-architecture trade-offs across features, performance, power, and area.</li><li>Define clean interfaces and deliver production-quality RTL (Verilog/SystemVerilog).</li><li>Implement and verify designs at both block and subsystem levels (using UVM/formal as needed); set coverage goals and drive sign-off.</li><li>Define constraints and close timing: author SDC, run STA (setup/hold, OCV/derates), perform CDC/RDC analysis, and collaborate with PD on floorplanning and CTS.</li><li>Perform simulation and emulation (FPGA/emulator), debug waveforms/logs, and correlate pre- and post-silicon behavior.</li><li>Define and implement DFT/DFD strategies (scan, MBIST/LBIST, boundary scan/JTAG); support ATPG and test bring-up.</li><li>Maintain high code quality with lint, CDC/RDC, LEC, and synthesis-friendly design practices; manage ECOs where necessary.</li><li>Build automation flows: develop Tcl/PrimeTime scripts for skew analysis, clocking, and core-to-IO interfaces (PCIe, 400GE, UCIe).</li><li>Write clear specifications, micro-architecture docs, and user guides for downstream engineering teams.</li></ul>
<b>Technologies:</b>
<ul><li>AI</li><li>Ethernet</li><li>FPGA</li><li>Firmware</li><li>Support</li><li>PCIe</li><li>Python</li><li>SystemVerilog</li><li>Verilog</li><li>Flow</li><li>Linux</li><li>Security</li></ul>
<p><b>More:</b></p>
<p>We are seeking a Senior ASIC Design Engineer to own the end-to-end design of critical AI ASIC subsystems. The RTL you create will become production silicon, powering real-world AI workloads faster and more efficiently. In this role, you will collaborate closely with silicon architects, verification engineers, firmware engineers, and other teams to ensure design robustness and optimize workload mapping. We value deep RTL mastery and the ability to integrate complex IP while driving architectural decisions in our innovative environment.</p>
<p>last updated 8 week of 2026</p>