Principal Verification Engineer

<p><b>Salary: £65,000 - 105,000 per year</b></p>
<b>Requirements:</b>
<ul><li>8 years in digital design verification with leadership experience</li><li>Strong SystemVerilog/UVM skills</li><li>Full verification lifecycle experience through tapeout</li><li>C and/or Python for test automation</li><li>Git/GitHub and team collaboration experience</li><li>Nice to Have: Formal verification, RISC-V/ISA experience, security verification, post-silicon debug</li></ul>
<b>Responsibilities:</b>
<ul><li>Lead design, implementation, and debugging of SystemVerilog/UVM testbenches</li><li>Develop verification plans, tests, and coverage strategies</li><li>Mentor engineers and drive best practices</li><li>Collaborate with partners to support successful tapeouts</li><li>Contribute to test and CI infrastructure</li></ul>
<b>Technologies:</b>
<ul><li>Git</li><li>GitHub</li><li>Support</li><li>Python</li><li>Security</li><li>SystemVerilog</li></ul>
<p><b>More:</b></p>
<p>We have an exciting opportunity in Cambridge for a Principal Verification Engineer to lead the verification of open-source digital designs, including OpenTitan, RISC-V cores, OTBN, crypto accelerators, and peripherals. Our team values collaboration and innovation, and we are committed to driving best practices in the industry.</p>
<p>last updated 8 week of 2026</p>